1. Field of the Invention
This invention relates to a solid electrolytic capacitor such as tantalum capacitor or aluminum capacitor which is designed for realizing both a size reduction and a capacitance increase. The present invention also relates to a method of making such a capacitor.
2. Description of the Prior Art
A solid electrolytic capacitor such as tantalum capacitor or aluminum capacitor is known to provide a large capacitance with a small size. Typically, such a capacitor is manufactured in the following manner.
First, as shown in FIG. 31 of the accompanying drawings, metal particles (e.g. tantalum particles) are compacted and sintered into a porous chip 2 which has a metallic anode wire 3 (made of e.g. tantalum) partially embedded in and partially projecting from the chip 2.
Then, as shown in FIG. 32, the porous chip 2 together with a root portion of the wire 3 is immersed in an aqueous solution A of phosphoric acid and subjected to anodic oxidation (electrolytic oxidation) by applying a direct current. As a result, a dielectric coating (made of e.g. tantalum pentoxide) is formed on the surfaces of the metal particles and on the immersed root of the wire 3. In FIG. 32, only the exposed portion of the dielectric coating is schematically represented by reference numeral 4 in an exaggerated manner for purposes of illustration, and an excess portion of the exposed dielectric coating 4 formed on the root of the wire 3 and having a height H is represented by reference sign 4a.
Then, as shown in FIG. 33, the dielectrically coated chip 2 is immersed in an aqueous solution B of manganese nitrate to cause permeation of the solution into the porous chip portion, and thereafter taken out of the solution for baking. This step is repeated plural times to fill the inner voids or pores of the chip 2 with a solid electrolyte (e.g. manganese dioxide) while also forming an exposed solid electrolyte layer 5 over the exposed dielectric coating 4. Alternatively, the solid electrolyte may be made of an organic semiconductor substance which is obtained by chemical polymerization, electrolytic oxidative polymerization or gas phase polymerization.
Then, a metallic cathode layer (not shown) is formed on the solid electrolyte layer 5 (FIG. 33) usually with an intervening layer or layers (e.g. graphite layer) interposed between the cathode layer and the electrolyte layer. A capacitor element 1 is thus obtained.
According to the prior art described above, the excess portion 4a of the dielectric coating 4 on the root of the anode wire 3 is necessary for electrically separating (insulating) between the anode wire 3 and the solid electrolytic substance (namely, the cathode). If the anode wire 3 is cut off at the root thereof, it will be impossible to connect the anode (namely, the metal particles) of the capacitor to an external circuit. Thus, the anode wire 3 of the prior art capacitor must not be cut off at the root thereof.
In an actual product, therefore, the capacitor element 1 (including the chip 2 and the anode wire 3) is entirely enclosed in a resin package 7, as shown in FIG. 34 and disclosed in Japanese Patent Publication No. 3-30977. In this case, the unillustrated cathode layer formed on the chip 2 is held in electrical contact with a cathode terminal lead 6a, whereas the anode wire 3 is held in electrical contact with an anode terminal lead 6b. The respective terminal leads 6a, 6b project out of the package 7 and are bent toward the underside of the package 7 for conveniently mounting to a surface of a circuit board.
Obviously, the need for entirely enclosing both the chip 2 and the anode wire 3 in the resin package 7 inevitably leads to an increase in the overall size and weight of the capacitor. Thus, the capacitance per unit volume of the packaged capacitor cannot be increased as intended even if the capacitance per unit volume of the capacitor element 1 itself is large.
Further, large stresses are likely to be applied to the chip 2 and the related components 3, 6a, 6b at the time of molding the resin package 7. Therefore, the capacitor may be unexpectedly damaged (resulting in shorting or an increase of leak current) to cause a decreased production yield.
Moreover, the use of the resin package 7 and terminal leads 6a, 6b involves a relatively high material cost, which result in a production cost increase. The cost increase problem is also caused by the fact that the terminal leads 6a, 6b require additional steps of attaching and bending them.
In an alternative prior art arrangement shown in FIG. 35, the capacitor element 1 is partially enclosed in a resin package 8 with a part of the chip 2 exposed and with a tip portion of the anode wire 3 projecting out. The exposed part of the chip 2 is formed with a cathode terminal layer, whereas a deposit of e.g. solder is formed at the projecting tip of the anode wire 3 for working as an anode terminal.
While the alternative arrangement eliminates some of the problems associated with the arrangement of FIG. 34, the size and weight reduction achievable by the alternative arrangement is still insufficient because the anode wire 3 must be retained.